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? 2003 quicklogic corporation www.quicklogic.com ? 1 ? device highlights high performance and high density 4,000 usable pld gates with 82 i/os 300 mhz 16-bit counters, 400 mhz datapaths 0.35 m four-layer metal non-volatile cmos process for smallest die sizes easy-to-use / fast development cycles 100% routable with 100% utilization and complete pin-out stability variable-grain logic cells provide high performance and 100% utilization comprehensive design tools include high quality verilog/vhdl synthesis advanced i/o capabilities interfaces with 3.3 and 5.0 v devices pci compliant with 3.3 and 5.0 v buses for -1/-2/-3/-4 speed grades full jtag boundary scan i/o cells with indivi dually controlled registered input path and output enables total of 82 i/o pins 74 bidirectional input/output pins, pci-compliant for 3.3 and 5.0 v buses for -1/-2/-3/-4 speed grades four high-drive input-only pins four high-drive/distributed network pins four low-skew distributed networks two array clock/control networks available to the logic cell flip-flop clock, set and reset inputs ? each driven by an input-only pin two global clock/control networks available to the logic cell; f1, clock, set and reset inputs and the data input, i/o register clock, reset and enable inputs as well as the output enable control ? each driven by an input- only or i/o pin, or any logic cell output or i/o cell feedback high performance input + logic cell + output total delays under 6 ns data path speeds over 400 mhz counter speeds over 300 mhz figure 1: 96 pasic 3 logic cells ql3004e pasic 3 fpga data sheet 4,000 usable pld gate pasic 3 fpga combining high performance and high density
www.quicklogic.com ? 2003 quicklogic corporation ql3004e pasic 3 fpga data sheet rev c 2 architecture overview the ql3004e is a 4,000 usable pld gate member of the pasic 3 family of fpgas. pasic 3 fpgas are fabricated on a 0.35 m four-layer metal process using quicklogic ? patented vialink ? technology to provide a unique comb ination of high performance, high density, low cost, and extreme ease-of-use. the ql3004e contains 96 logic cells. with a ma ximum of 74 i/os, the ql3004e is available in 68-pin plcc, 84-pin plcc, and 100-pin tqfp packages. software support for the complete pasic 3 family, including the ql3004e, is available through three basic packages. the turnkey quick works ? package provides the most complete fpga software solution from design entry to logic synthesis, to place and route, to simulation. the quicktools tm for workstations package provides a solution for designers who use cadence ? , exemplar tm , mentor ? , synopsys ? , synplicity ? , viewlogic tm , aldec tm , or other third-party tools for design entry, synthesis, or simulation. electrical specifications ac characteristics at v cc = 3.3 v, ta = 25 c (k = 1.00) to calculate delays, multiply the appropriate k factor from table 7 by the numbers provided in table 1 through table 5 . table 1: logic cells symbol parameter propagation delays (ns) fanout a a. stated timing for worst case propagation delay over process variation at v cc = 3.3 v and ta = 25 c. multiply by the appropriate delay factor, k, for speed grade, vo ltage, and temperature settings as specified in table 7 . 1 2 3 4 8 t pd combinatorial delay b b. these limits are derived from a representative selection of the slowest paths through the pasic 3 logic cell including typical net delays. wo rst case delay values for specific paths should be determined from timing analysis of your particular design. 1.4 1.7 1.9 2.2 3.2 t su setup time b 1.7 1.7 1.7 1.7 1.7 t h hold time 0.0 0.0 0.0 0.0 0.0 t clk clock to q delay 0.7 1.0 1.2 1.5 2.5 t cwhi clock high time 1.2 1.2 1.2 1.2 1.2 t cwlo clock low time 1.2 1.2 1.2 1.2 1.2 t set set delay 1.0 1.3 1.5 1.8 2.8 t reset reset delay 0.8 1.1 1.3 1.6 2.6 t sw set width 1.9 1.9 1.9 1.9 1.9 t rw reset width 1.8 1.8 1.8 1.8 1.8
? 2003 quicklogic corporation www.quicklogic.com ql3004e pasic 3 fpga data sheet rev c 3 table 2: input-only/clock cells symbol parameter propagation delays (ns) fanout a a. stated timing for worst case propagatio n delay over process variation at v cc = 3.3 v and ta = 25 c. multiply by the appropriate delay factor , k, for speed grade, vo ltage, and temperature settings as specified in table 7 . 1 2 3 4 8 12 24 t in high drive input delay 1.5 1.6 1.8 1.9 2.4 2.9 4.4 t ini high drive input, inverting delay 1.6 1.7 1.9 2.0 2.5 3.0 4.5 t isu input register set-up time 3.1 3.1 3.1 3.1 3.1 3.1 3.1 t ih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 t lclk input register clock to q 0.7 0.8 1.0 1.1 1.6 2.1 3.6 t lrst input register reset delay 0.6 0.7 0.9 1.0 1.5 2.0 3.5 t lesu input register clock enable set-up time 2.3 2.3 2.3 2.3 2.3 2.3 2.3 t leh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 table 3: clock cells symbol parameter propagation delays (ns) loads per half column a a. the array distributed networks consist of 24 half columns and the global distributed networks consist of 28 half columns, each driven by an independent buffer. the number of half columns used does not affect clock buffer delay. the array clock has up to eight loads per half column. the global clock has up to seven loads per half column. 1 2 3 4 8 10 11 t ack array clock delay 1.2 1.2 1.3 1.3 1.5 1.6 1.7 t gckp global clock pin delay 0.7 0.7 0.7 0.7 0.7 0.7 0.7 t gckb global clock buffer delay 0.8 0.8 0.9 0.9 1.1 1.2 1.3
www.quicklogic.com ? 2003 quicklogic corporation ql3004e pasic 3 fpga data sheet rev c 4 figure 2: loads used for t pxz table 4: input-only i/o cells symbol parameter propagation delays (ns) fanout a 1 2 3 4 8 10 t i/o input delay (bidirectional pad) 1.3 1.6 1.8 2.1 3.1 3.6 t isu input register set-up time 3.1 3.1 3.1 3.1 3.1 3.1 t ih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 t loclk input register clock to q 0.7 1.0 1.2 1.5 2.5 3.0 t lorst input register reset delay 0.6 0.9 1.1 1.4 2.4 2.9 t lesu input register clock enable set-up time 2.3 2.3 2.3 2.3 2.3 2.3 t leh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 a. stated timing for worst case propaga tion delay over process variation at v cc = 3.3 v and ta = 25 c. multiply by the appropriate delay factor, k, for speed grade, voltage, and temperature settings as specified in table 7 . table 5: output-only i/o cells symbol parameter propagation delays (ns) output load capacitance (pf) 30 50 75 100 150 t outlh output delay low to high 2.1 2.5 3.1 3.6 4.7 t outhl output delay high to low 2.2 2.6 3.2 3.7 4.8 t pzh output delay tri-state to high 1.2 1.7 2.2 2.8 3.9 t pzl output delay tri-state to low 1.6 2.0 2.6 3.1 4.2 t phz output delay high to tri-state a 2.0 - - - - t plz output delay low to tri-state 1.2 - - - - a. the loads presented in figure 2 are used for t pxz : 1? 1? t phz t plz 5 pf 5 pf
? 2003 quicklogic corporation www.quicklogic.com ql3004e pasic 3 fpga data sheet rev c 5 dc characteristics the dc specifications are provided in table 6 through table 8 . table 6: absolute maximum ratings parameter value parameter value v cc voltage -0.5 v to 4.6 v dc input current 20 ma v ccio voltage -0.5 v to 7.0 v esd pad protection 2000 v input voltage -0.5 v to v ccio +0.5 v storage temperature -65c to +150c latch-up immunity 200 ma lead temperature 300c table 7: operating range symbol parameter military industrial commercial unit min max min max min max v cc supply voltage 3.0 3.6 3.0 3.6 3.0 3.6 v v ccio i/o input tolerance voltage 3.0 5.5 3.0 5.5 3.0 5.25 v ta ambient temperature -55 - -40 85 0 70 c tc case temperature - 125 - - - - c k delay factor -0 speed grade - - 0.43 1.90 0.46 1.85 n/a -1 speed grade 0.42 1.64 0.43 1.54 0.46 1.50 n/a -2 speed grade 0.42 1.37 0.43 1.28 0.46 1.25 n/a -3 speed grade 0.43 0.90 0.46 0.88 n/a -4 speed grade 0.43 0.82 0.46 0.80 n/a
www.quicklogic.com ? 2003 quicklogic corporation ql3004e pasic 3 fpga data sheet rev c 6 table 8: dc characteristics symbol parameter conditions min max units v ih input high voltage 0.5 v cc v ccio +0.5 v v il input low voltage -0.5 0.3 v cc v v oh output high voltage ioh = -12 ma 2.4 v ioh = -500 a 0.9 v cc v v ol output low voltage iol = 16 ma a a. applies only to -1/-2/-3/-4 commercial grade devi ces. these speed grades are also pci-compliant. all other devices have 8 ma iol specifications. 0.45 v iol = 1.5 ma 0.1 v cc v i i i or i/o input leakage current vi = v ccio or gnd -10 10 a i oz 3-state output leakage current vi = v ccio or gnd -10 10 a c i input capacitance b b. capacitance is sample tested only. clock pins are 12 pf maximum. 10 pf i os output short circuit current c c. only one output at a time. duration should not exceed 30 seconds. vo = gnd -15 -180 ma vo = v cc 40 210 ma i cc d.c. supply current d d. for -1/-2/-3/-4 commercial grade devices only. maximum i cc is 3 ma for -0 commercial grade and all industrial grade devices, and 5 ma for all military grade devices. for ac conditions, contact quicklogic customer applications group (see ?c ontact information? on page 16). vi, vio = v ccio or gnd 0.50 (typ) 2 ma i ccio d.c. supply current on v ccio 0 100 a
? 2003 quicklogic corporation www.quicklogic.com ql3004e pasic 3 fpga data sheet rev c 7 kv and kt graphs figure 3: voltage factor vs. supply voltage figure 4: temperature factor vs. operating temperature 0.9200 0.9400 0.9600 0.9800 1.0000 1.0200 1.0400 1.0600 1.0800 1.1000 3 3.1 3.2 3.3 3.4 3.5 3.6 voltage factor vs. supply voltage supply voltage (v) kv 0.85 0.90 0.95 1.00 1.05 1.10 1.15 -60 -40 -20 0 20 40 60 80 temperature factor vs. operating temperature junction temperature c kt
www.quicklogic.com ? 2003 quicklogic corporation ql3004e pasic 3 fpga data sheet rev c 8 power-up sequencing figure 5: power-up requirements when powering up a device, the v cc /v ccio rails must take 400 s or longer to reach the maximum value (refer to figure 5 ). note: ramping v cc /v ccio to the maximum voltage faster than 400 s can cause the device to behave improperly. for users with a limited power budget, keep (v ccio -v cc ) max 500 mv when ramping up the power supply. voltage v ccio v cc (v ccio -v cc ) max time 400 us v cc
? 2003 quicklogic corporation www.quicklogic.com ql3004e pasic 3 fpga data sheet rev c 9 jtag figure 6: jtag block diagram microprocessors and application specific inte grated circuits (asics) pose many design challenges, not the least of which concerns the acce ssibility of test points. the joint test access group (jtag) formed in response to this chal lenge, resulting in ieee standard 1149.1, the standard test access port and boundary scan architecture. the jtag boundary scan test methodology allo ws complete observation and control of the boundary pins of a jtag-compa tible device through jtag software. a test access port (tap) controller works in concert with the instructi on register (ir); these allow users to run three required tests, along with several user-defined tests. jtag tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements. tck tms trstb rdi tdo instruction decode & control logic tap controller state machine (16 states) instruction register boundary-scan register (data register) mux bypass register mux internal register i/o registers user defined data register
www.quicklogic.com ? 2003 quicklogic corporation ql3004e pasic 3 fpga data sheet rev c 10 the 1149.1 standard requires the following three tests: extest instruction. the extest instruction performs a printed circuit board (pcb) interconnect test. this test places a device into an external boundary test mode, selecting the boundary scan register to be connected between the tap test data in (tdi) and test data out (tdo) pins. boundary scan cells are preloaded with test patterns (via the sample/preload instruction), and input boundary cells capture the inpu t data for analysis. sample/preload instruction. the sample/preload instruction allows a device to remain in its functional mode, while selecting the boun dary scan register to be connected between the tdi and tdo pins. for this test, the boundary scan register can be accessed via a data scan operation, allowing users to sample the fu nctional data entering and leaving the device. bypass instruction. the bypass instruction allows data to skip a device boundary scan entirely, so the data passes th rough the bypass register. the bypass instruction allows users to test a device without passing through othe r devices. the bypass register is connected between the tdi and tdo pins, allowing serial data to be transferred through a device without affecting the operation of the device.
? 2003 quicklogic corporation www.quicklogic.com ql3004e pasic 3 fpga data sheet rev c 11 pin descriptions table 9: pin descriptions pin function description tdi test data in for jtag hold high during normal operation. connect to v cc if not used for jtag. trstb active low reset for jtag hold low during normal operation. connect to ground if not used for jtag. tms test mode select for jtag hold high during normal operation. connect to v cc if not used for jtag. tck test clock for jtag hold high or low during normal operation. connect to v cc or ground if not used for jtag. tdo test data out for jtag output that must be left unconnected if not used for jtag. stm special test mode must be grounded during normal operation. i/aclk high-drive input and/or array network driver can be configured as either or both. i/gclk high-drive input and/or global network driver can be configured as either or both. i high-drive input use for input signals with high fanout. i/o input/output pin can be configured as an input and/or output. v cc power supply pin connect to 3.3 v supply. v ccio input voltage tolerance pin connect to 5.0 v supply if 5.0 v input tolerance is required, otherwise connect to 3.3 v supply. gnd ground pin connect to ground.
www.quicklogic.com ? 2003 quicklogic corporation ql3004e pasic 3 fpga data sheet rev c 12 68 plcc pinout diagram figure 7: top view of 68 pin plcc 68 plcc pinout table table 10: 68 plcc pinout table 68 plcc function 68 plcc function 68 plcc function 68 plcc function 1 gnd 18 v cc 35 gnd 52 v cc 2 i/o 19 i 36 i/o 53 i 3 i/o 20 gclk/i 37 i/o 54 gclk/i 4 v ccio 21 i/o 38 i/o 55 i/o 5 i/o 22 i/o 39 v ccio 56 i/o 6 i/o 23 i/o 40 i/o 57 i/o 7 i/o 24 i/o 41 i/o 58 i/o 8 i/o 25 i/o 42 trstb 58 i/o 9 tdo 26 i/o 43 tms 60 i/o 10 i/o 27 tdi 44 i/o 61 tck 11 i/o 28 i/o 45 i/o 62 stm 12 i/o 29 i/o 46 i/o 63 i/o 13 i/o 30 i/o 47 i/o 64 i/o 14 gnd 31 i/o 48 gnd 65 i/o 15 i/o 32 i/o 49 i/o 66 i/o 16 i 33 i/o 50 i 67 i/o 17 aclk/i 34 i/o 51 aclk/i 68 i/o tdo io io io io vccio io io gnd io io io io io io stm tck io io io io io io gclk/i i vcc aclk/i i io gnd io io io io tdi io io io io io io io gnd io io io vccio io io trstb tms 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 ql3004e-1pl68c pasic 3 io io io io gnd io i aclk/i vcc i gclk/i io io io io io io 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
? 2003 quicklogic corporation www.quicklogic.com ql3004e pasic 3 fpga data sheet rev c 13 84 plcc pinout diagram figure 8: top view of 84 pin plcc 84 plcc pinout diagram table 11: 84 plcc pinout diagram 84 plcc function 84 plcc function 84 plcc function 84 plcc function 1 i/o 22 aclk/i 43 i/o 64 aclk/i 2 i/o 23 i 44 i/o 65 i 3 i/o 24 gclk/i 45 i/o 66 gclk/i 4 v ccio 25 v cc 46 v ccio 67 vcc 5 i/o 26 i/o 47 i/o 68 i/o 6 i/o 27 i/o 48 i/o 69 i/o 7 i/o 28 i/o 49 i/o 70 i/o 8 i/o 29 i/o 50 i/o 71 i/o 9 i/o 30 i/o 51 i/o 72 i/o 10 i/o 31 i/o 52 trstb 73 i/o 11 tdo 32 i/o 53 tms 74 i/o 12 i/o 33 tdi 54 i/o 75 tck 13 i/o 34 i/o 55 i/o 76 stm 14 i/o 35 i/o 56 i/o 77 i/o 15 i/o 36 v cc 57 i/o 78 i/o 16 i/o 37 i/o 58 i/o 79 v cc 17 i/o 38 i/o 59 i/o 80 i/o 18 i/o 39 i/o 60 i/o 81 i/o 19 gnd 40 gnd 61 gnd 82 gnd 20 i/o 41 i/o 62 i/o 83 i/o 21 i 42 i/o 63 i 84 i/o tdo io io io io io io vccio io io io io io gnd io io vcc io io stm tck io io io io io io io vcc gclk/i i aclk/i i io gnd io io io io io io io tdi io io vcc io io io gnd io io io io io vccio io io io io io trstb tms 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ql3004e-1pl84c pasic 3 io io io io io io io gnd io i aclk/i i gclk/i vcc io io io io io io io 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
www.quicklogic.com ? 2003 quicklogic corporation ql3004e pasic 3 fpga data sheet rev c 14 100 tqfp pinout diagram figure 9: top view of 100 pin tqfp pin 1 pin 26 pin 51 pin 76 ql3004e-1pf100c pasic 3
? 2003 quicklogic corporation www.quicklogic.com ql3004e pasic 3 fpga data sheet rev c 15 100 tqfp pinout table table 12: 100 tqfp pinout table 100 tqfp function 100 tqfp function 100 tqfp function 100 tqfp function 1 i/o 26 tdi 51 i/o 76 tck 2 i/o 27 i/o 52 i/o 77 stm 3 i/o 28 i/o 53 i/o 78 i/o 4 i/o 29 i/o 54 i/o 79 i/o 5 i/o 30 i/o 55 i/o 80 i/o 6 i/o 31 i/o 56 i/o 81 i/o 7 i/o 32 i/o 57 i/o 82 i/o 8 i/o 33 i/o 58 i/o 83 i/o 9 gnd 34 i/o 59 gnd 84 i/o 10 i/o 35 gnd 60 i/o 85 gnd 11 i 36 i/o 61 i 86 i/o 12 aclk / i 37 i/o 62 aclk / i 87 i/o 13 v cc 38 gnd 63 v cc 88 gnd 14 i 39 i/o 64 i 89 i/o 15 gclk / i 40 i/o 65 gclk / i 90 i/o 16 v cc 41 i/o 66 v cc 91 i/o 17 i/o 42 v ccio 67 i/o 92 v ccio 18 i/o 43 i/o 68 i/o 93 i/o 19 i/o 44 i/o 69 i/o 94 i/o 20 i/o 45 i/o 70 i/o 95 i/o 21 i/o 46 i/o 71 i/o 96 i/o 22 i/o 47 i/o 72 i/o 97 i/o 23 i/o 48 i/o 73 i/o 98 i/o 24 i/o 49 trstb 74 i/o 99 i/o 25 i/o 50 tms 75 i/o 100 tdo
www.quicklogic.com ? 2003 quicklogic corporation ql3004e pasic 3 fpga data sheet rev c 16 ordering information * contact quicklogic regarding availability (see ?contact information? on page 16). contact information telephone: (408) 990 4000 (us) (416) 497 8884 (canada) +(44) 1932 57 9011 (rest of europe) +(49) 89 930 86 170 (germany & benelux) +(8621) 2890 3029 (asia) +(81) 45 470 5525 (japan) e-mail: info@quicklogic.com support: http://www.quicklogic.com/support web site: http://www.quicklogic.com/ ql 3004e - 1 pf100 c quicklogic device pasic 3 device part number speed grade 0 = quick 1 = fast 2 = faster 3 = faster *4 = wow operating range c = commercial i = industrial m = military package code pl68 = 68-pin plcc pl84 = 84-pin plcc pf100 = 100-pin tqfp
? 2003 quicklogic corporation www.quicklogic.com ql3004e pasic 3 fpga data sheet rev c 17 revision history copyright and trademark information copyright ? 2003 quicklogic corporation. all rights reserved. the information contained in this document and the accompanying software programs is protected by copyright. all rights are reserv ed by quicklogic corporation. quicklogic corporation reserves the right to modify this document without any obligation to notify any person or entity of such revision. copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representa tive of quicklogic is prohibited. quicklogic and the quicklogic logo, pasic, vialink, deskfab, and quickworks are registered trademarks of quicklogic corp oration; eclipse, quickfc, quickdsp, quickdr, quicksd, quicktools, quickcore, quickpro, spde, webasic, and webesp are trademarks of quicklogic corporation. table 13: revision history revision date comments a january 2003 brian faith and andreea rotaru b april 2003 brian faith and kathleen murchek c july 2003 brian faith and kent holman

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